Semiconductor devices, such as field effect transistor (FET)-type semiconductor devices (e.g., metal-oxide semiconductor FETs (MOSFETs), junction-gate semiconductor FETs (JFETs), etc.), as well as bipolar junction transistor (BJT) and insulated-gate bipolar transistor (IGBT) devices use the conductive properties of semiconductor materials. Such semiconductor materials may include, for example, silicon (Si) or silicon-containing materials, graphene, germanium (Ge), gallium arsenide (GaAs), or gallium nitride (GaN).
In particular, GaN FET semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to be switched up to ten times faster than commercial MOSFETs, as well as carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages while operating at high frequencies.
One example of a GaN FET device is a GaN HEMT device, which may include a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
In a GaN semiconductor device, the nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because of the 2DEG region existing under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide. An enhancement mode device requires a positive bias applied at the gate in order to conduct current. Examples of GaN semiconductor devices can be found in commonly assigned U.S. Patent Application Publication Nos. 2010/0258912 and 2010/0258843, both of which are incorporated by reference in their entirety.
FIG. 1A illustrates a cross-sectional view of one example of an enhancement mode GaN transistor device 100. Commonly assigned U.S. Patent Application Publication No. 2010/0258843 discloses one example of a process for forming such a device. In FIG. 1, device 100 includes substrate 101, which may be either sapphire, SiC, or silicon, transition layers 102, un-doped GaN material 103, un-doped AlGaN barrier material 104, drain ohmic contact metal 110, source ohmic contact metal 111, a doped p-type AlGaN or p-type GaN layer formed into a doped epitaxial gate 113, and gate metal 112 formed over the doped epitaxial gate 113. A layer of dielectric material 105, such as silicon nitride, covers the barrier material 104, such that a portion 114 of the dielectric material covers gate 113.
FIG. 1B illustrates a top-down view of the transistor device 100, including the location of the gate metal 112. The lettering of transistor device 100 in FIG. 1B is used throughout this description to illustrate the orientation of respective transistor devices. For example, in transistor device 100, source ohmic contact metal 111 may be located on one side (e.g., a right side) of transistor device 100, while drain ohmic contact metal 110 may be located on the other side (e.g., a left side) of transistor device 100.
Transistor devices are often used in devices requiring high current capability and fast switching capability, such as RF amplifiers, switching converters, or other circuits. A well known technique for increasing current-handling capabilities of devices is to use multiple transistors devices connected in parallel. Paralleling of transistor devices increases their current capability, thereby increasing the power throughput of the circuit. Paralleling of transistor devices is also frequently used to distribute heat loss in devices.
Examples of paralleled transistors are described, for example, in U.S. Pat. No. 7,330,046, entitled “Circuits and Methods for Failure Prediction of Parallel MOSFETs,” and, for example, in J. Forsythe, International Rectifier, “Paralleling of Power MOSFETs for higher Power Output,” which are hereby incorporated by reference in their entirety. Examples of RF applications of paralleled transistors are described, for example, in H. Granberg, Motorola Inc. Engineering Bulletin EB 104, “GET 600 WATTS RF FROM FOUR POWER FETs” (1983), and R. Frey, Microsemi Power Products Group Application Note 1814, “Paralleling MOSFETs in RF Amplifiers” (2010), which are hereby incorporated by reference in their entirety.
One common application for paralleled transistor devices is a switching device including a paralleled group of transistors (e.g., GaN transistors) configured to act as a single transistor. The paralleled transistors may include a single gate driver for the switching device.
FIG. 2 illustrates one example of a conventional design layout for a paralleled switching circuit 120. Circuit 120 includes four pairs of parallel transistor devices Qupper1, Qupper2, Qupper3, Qupper4, Qlower1, Qlower2, Qlower3, Qlower4, each of which may be, for example, GaN FET transistor devices, MOSFET transistor devices, or other transistor devices known in the art. The parallel transistor devices Qupper1, Qupper2, Qupper3, Qupper4, Qlower1, Qlower2, Qlower3, Qlower4, are formed on a single side of a printed circuit board (PCB). Upper parallel transistor devices Qupper1, Qupper2, Qupper3, and Qupper4 are driven by a common gate transfer control line 212, and lower parallel transistor devices Qlower1, Qlower2, Qlower3, Qlower4 are driven by a common gate transfer control line 214. Each set of upper and lower transistors in circuit 120 includes one or more respective decoupling capacitors 202, 204, 206, 208. A switch node current 216 of circuit 120 (i.e., an output current) exits circuit 120 in a lengthwise direction.
In the design of a paralleled switching circuit, or any other circuit including paralleled transistor devices, however, numerous factors must be accounted for to realize an efficient and reliable circuit. In particular, different types of transistor devices have different requirements and design considerations for implementation in parallel circuits. For example, when paralleling GaN FETs, the characteristics of the GaN transistors to be used must be considered. Most notably, the selection of devices, such as whether to use more small devices or fewer large devices to achieve the desired circuit parameters, whether the selected devices have positive or negative temperatures coefficients for certain key characteristics, such as threshold voltage Vth and drain-source resistance RDSon, and whether part-to-part and/or lot-to-lot variations may affect the overall design.
Another consideration for designing transistor devices, and in particular GaN FET semiconductor devices, is the layout of the circuit. Layout designs should take into account various factors including printed circuit board (PCB) restrictions (including board populating) and placement and routing design. In addition, GaN semiconductor devices require additional considerations due to their small size, compact connection structure, and high demand on specifications such as current and voltage.
Another area that must be considered is the parameters of the circuits themselves. Circuits employing FET devices typically require certain circuit changes to ensure maximum performance from each of the devices, and to ensure that the paralleled switch can function at near theoretical maximum performance.
For example, one parameter that must be controlled is the Miller capacitances in the circuit. The Miller capacitance represents the increased equivalent input capacitance in an amplifier due to amplification of capacitance between the input and output terminals of the amplifier. In a transistor, Miller capacitance is driven by the rate of change over time of the voltage (dv/dt) of the transistor. Miller capacitance can induce a current into the gate path during switching events.
As another example, because GaN transistor devices are designed to have increased switching frequency and improved packaging, they are particularly sensitive to common source inductance (CSI). CSI is a parasitic inductance at a common source node, which can generate a voltage that is shared by the drain-to-source current path and the gate driver loop of a transistor device. In a transistor, CSI is dependent upon the rate of change over time of the current (di/dt) flowing through the transistor. CSI can induce unwanted gate voltages into a transistor device. Common source inductance between paralleled transistors is described, for example, in A. Elbanhawy, Fairchild Semiconductor Application Note AN-7019, “Limiting Cross-Conduction Current in Synchronous Buck Converter Designs” (Rev. A. 2005), which is hereby incorporated by reference in its entirety.
FIG. 3 illustrates the effect of CSI in a circuit 150 including a pair of parallel transistor devices Q1, Q2, which may be, for example, GaN FET transistor devices, connected in parallel. A first transistor device Q1 includes parasitic capacitances including drain-to-source capacitance Cds1, gate-to-drain capacitance Cgd1, and gate-to-source capacitance Cgs1. A second transistor device Q2 includes parasitic capacitances including drain-to-source capacitance Cds2, gate-to-drain capacitance Cgd2, and gate-to-source capacitance Cgs2. The gates of first and second transistor devices Q1, Q2 are electrically connected to a common voltage driver VGateDrive via respective gate transfer control lines 222, 224. Each gate transfer control line 222, 224 includes a respective gate transfer control line inductance LG1, LG2. First and second transistor devices Q1, Q2 may be, for example, low-side transistors in a switching device, with their drains connected to one or more upper-side transistors QUpperSW.
First and second transistor devices Q1, Q2 share a common source node 216 that experiences parasitic common source inductances LCSP1 and LCSP2 connected in series with LCSG1 and LCSG2, respectively. FIG. 3 shows one example of a gate driver loop current Idv/dt that may be formed as a result of the Miller capacitances of transistor device Q1, and a gate voltage Vdi/dt that may be generated as a result of common source inductance LCSP1 of transistor device Q1. As shown in circuit 150, the source current IL_CS of first transistor device Q1 flows through the common source inductance LCSP1, creating a voltage Vdi/dt at the gate of transistor device Q1 when source current IL_CS is transient. Because voltage Vdi/dt affects the voltage on the gate driver loop of transistor devices Q1, Q2, a change of source current IL_CS (e.g., during transient events) may undesirably affect operation of one or both of transistor devices Q1, Q2. For example, in some cases, voltage Vdi/dt could turn transistor device Q1 and/or transistor device Q2 on and/or off unexpectedly. In other cases, voltage Vdi/dt could potentially overload the voltage at the respective gates when transistor devices Q1, Q2 are turned on. Particularly for GaN devices and other semiconductor devices with high switching frequency capability and/or frequent current transients, it is desirable to maintain a low common source inductance. It is further beneficial to prevent unexpected gate turn on for Q1 during a high dv/dt event that can inject current into the gate driver loop via Miller capacitances. Keeping the common source inductance low also keeps the gate loop impedance low, thereby raising the threshold magnitude of the Miller-induced current that will corrupt the gate of the transistor.
Accordingly, there is a need and desire for a semiconductor device, circuit, layouts for such devices, and methods of forming such devices and circuits, that experience reduced negative effects from common source inductance, inter device inductance and other detrimental effects.